Design and implementation of a novel power optimized alu with 13t full adder (KEY IJP************477)

• V.priya Darshini,K.vanaja,K.hemanth,K.hariteja,J.n.s Narasimha Varma

Abstract

This paper presents a novel power-optimized Arithmetic Logic Unit (ALU) design that incorporates a novel full adder for improved efficiency. The proposed approach combines an X-NOR gate with the novel full adder to enhance performance and reduce power consumption compared to conventional designs. By integrating these components, we demonstrate the design of a 1-bit ALU, which is subsequently extended to an 8-bit ALU. The optimization results in reduced transistor count, lower power dissipation, and improved speed, making it suitable for low-power applications in modern electronic systems. The proposed ALU achieves efficient arithmetic and logical operations, offering a balance between power, area, and performance for advanced integrated circuits. Power optimization is achieved through the reduced transistor count of the full adder compared to traditional designs. Fewer transistors result in less power consumption during operation. Which contributes to creating a low-power, efficient ALU design that meets the demands of modern electronics where power efficiency, performance, and compactness are paramount. The use of advanced components like the proposed full adder and X-NOR gate makes it an innovative solution for future hardware design.