DESIGN AND ANALYSIS OF LOW POWER SRAM (KEY IJP************024)

• Nitin Kumari,Dr. Hitanshu

Abstract

SRAM, or static random access memory is essential to the functionality and energy efficiency of contemporary integrated circuits. It is becoming more and more important for SRAM to minimise power consumption as the market for portable, battery-operated products grows. An extensive examination of design approaches and analysis strategies for low-power SRAM implementations is presented in this study.The first part lists the essential variables affecting power consumption and describes the basic ideas behind SRAM functioning. It talks about the trade-offs between space, performance, and power and emphasises how important SRAM is to creating system designs that are energy-efficient.The following sections discuss several approaches to lower the power consumption of SRAM designs. Among these are circuit-level strategies like power gating, dynamic voltage and frequency scaling (DVFS), and voltage scaling. In addition, architectural optimisations are studied, including cache coherence techniques, bank-level power management, and hierarchical bitline architectures.Additionally, this work explores low-power optimised advanced SRAM cell designs. It investigates the effectiveness of methods for reducing both static and dynamic power dissipation, including subthreshold operation, multi-threshold voltage transistors, and decreased supply voltage. Moreover, thorough analytical techniques for assessing the trade-offs between power and performance in low-power SRAM architectures are provided. This includes methods for predicting energy consumption under different operating circumstances and workloads that are based on simulation as well as analytical models.