Designing Power-Efficient Flip-Flop Integrated Circuits for Very Large-Scale Integration (VLSI) (KEY IJP************784)

• Uditanshu S. Deshpande

Abstract

: Over the years, advancements in Very Large Scale Integration (VLSI) technology have increased the capabilities of integrated circuits in three primary areas: area, power consumption, and latency. The challenges of the nanoscale era of very large scale integration (VLSI) low power design and the impending demands of computing need novel approaches to digital logic design that are more efficient, less power hungry, and more resistant to noise fluctuation. Modern methods like Adiabatic Logic (ADL) and Gate Diffusion Input (GDI) seek to lessen the circuit's power consumption and delay time. A fascinating new approach to constructing power-efficient digital combinational circuits is the gate diffusion input (GDI). The GDI mechanism allows for a decrease in power consumption, propagation latency, and circuit size while maintaining a logic architecture with minimal complexity. To further guarantee low power consumption and simpler clock design, another innovative approach to designing combinational and sequential logic circuits is Single Phase Quasi-Static Adiabatic Dynamic Logic (SPADL). A single pulse source is used by SPADL, the supply clock. Reduced energy dissipation occurs across active devices as a result of this strategy's limited charge transfer and current restrictions